Packaging structure

ABSTRACT

A package structure and a package process are proposed in using pillar bumps to connect an upper second chip and through silicon vias of a lower first chip, wherein a gap between the first chip and the second chip can be controlled by adjusting a height of the pillar bumps. In other words, the pillar bumps compensate the height difference between the first chip and a molding compound surrounding the first chip so as to ensure the bondibility between the pillar bumps and the corresponding through silicon vias and improve the process yield. Furthermore, the pillar bumps maintain the gap between the second chip and the molding compound for allowing an underfill being properly filled into the space between the first chip and the second chip.

CROSS-REFERENCE TO RELATED APPLICATION

This is a continuation application of and claims the priority benefit ofa prior application Ser. No. 12/817,396, filed on Jun. 17, 2010, nowpending. The prior application Ser. No. 12/817,396 claims the prioritybenefit of Taiwan patent application serial no. 99116089, filed May 20,2010. The entirety of each of the above-mentioned patent applications ishereby incorporated by reference herein and made a part of thisspecification.

BACKGROUND OF THE INVENTION

The present invention relates to a package structure and a packageprocess, and particularly relates to a stacked package structure andfabricating process thereof.

In today's information society, users all seek after electronic productswith high speed, high quality and multiple functions. In terms of theproduct exterior appearance, electronic product designs reveal a trendof light weight, thinness and compactness. Therefore, varioussemiconductor device package techniques such as stacked semiconductordevice package technique are proposed.

In the stacked semiconductor device package technique, severalsemiconductor devices are perpendicularly stacked together to form apackage structure so that the package density is improved and thedimension of the package is decreased. Furthermore, by usingthree-dimensional stacking method to decrease the path length of thesignal transmission between the semiconductor devices, rate of thesignal transmission is improved and the semiconductor devices withdifferent functions can be combined in the same package.

A conventional stacked semiconductor device package process is proposedby disposing a chip carrier on a circuit substrate first, and then aplurality of through silicon vias (TSV) are fabricated in the chipcarrier after a molding process for electrically connecting asequentially stacked upper chip with the circuit substrate.

To a conventional fabrication method, the through silicon vias arefabricated by grinding the chip carrier and the molding compound abovethe chip carrier until a top surface of each of the through silicon viasis exposed. Next, a selective etching process is performed to protrudingan end of each of the through silicon vias from the chip carrier.However, the height of the chip carrier goes to be lower than that ofthe molding compound after the selective etching process is performed.For instance, the thickness of the chip carrier and the thickness of themolding compound being almost the same before the selective etchingprocess goes different after the selective etching process, wherein aheight difference between the chip carrier and the molding compoundreaches 3˜5 μm or even goes beyond 5 μm. If so, the height of bumps onthe upper chip may not satisfy the aforementioned height difference asbonding the upper chip to the chip carrier, such that a failure ofelectrical test occurs due to invalid bonding between the bumps and thethrough silicon vias, or the underfill can not be properly filled into arestricted space between the upper chip and the molding compound.

SUMMARY OF THE INVENTION

The present invention is directed to a package structure and a packageprocess, wherein reliable bonding effect between an upper chip andthrough silicon vias of a chip carrier of a stacked semiconductor devicepackage can be achieved to improve process yield.

The present invention is directed to a package structure and a packageprocess, wherein a favorable gap between an upper chip and a moldingcompound of a stacked semiconductor device package can be effectivelymaintained for accomplishing a sequent molding process.

As embodied and broadly described herein, a package structure comprisinga circuit substrate, a first chip, a plurality of first bumps, a firstmolding compound, a second chip and a plurality of pillar bumps isprovided. The circuit substrate comprises a top surface and a bottomsurface opposite to the top surface. The first chip is disposed on thetop surface of the circuit substrate. The first chip has a top surfaceand a bottom surface opposite to each other, wherein the bottom surfaceof the first chip faces the circuit substrate, and the first chip has aplurality of through silicon vias. An end of each of the through siliconvias protrudes from the top surface of the first chip. The first bumpsare disposed between the first chip and the circuit substrate andelectrically connecting the through silicon vias with the circuitsubstrate. The first molding compound covers the entire top surface ofthe circuit substrate and has an opening exposing the top surface of thefirst chip and the end of each of the through silicon vias. The secondchip is disposed above the first chip, and the second chip has a bottomsurface facing the first chip. The pillar bumps are disposed on thebottom surface of the second chip and electrically connecting the secondchip with the corresponding through silicon vias.

In an embodiment, the package structure further comprises a firstunderfill disposed between the first chip and the circuit substrate toencapsulate the first bumps.

In an embodiment, the package structure further comprises a secondmolding compound disposed on the first molding compound and covering thesecond chip.

In an embodiment, the package structure further comprises a secondunderfill disposed between the second chip and the first chip toencapsulate the pillar bumps and the end of each of the through siliconvias.

In an embodiment, a top surface of the first molding compound is higherthan the top surface of the first chip.

In an embodiment, a top surface of the first molding compound is higherthan the end of each of the through silicon vias.

In an embodiment, a top surface of the first molding compound has aheight difference H1 relative to the end of each of the through siliconvias, and a height H2 of the pillar bumps is greater than the heightdifference H1.

A package process is also provided herein. First, a circuit substratehaving a top surface is provided. Then, a plurality of first chips arebonded onto the top surface of the circuit substrate, wherein a bottomsurface of each of the first chips faces the circuit substrate, each ofthe first chips has a plurality of first bumps on the bottom surface ofthe first chip and a plurality of conductive vias, and each of the firstbumps electrically connects the corresponding conductive via with thecircuit substrate. Next, a first molding compound is formed to cover thetop surface of the circuit substrate and the first chips. Then, thefirst molding compound above each of the first chips is removed and thethickness of each of the first chips is reduced to expose a top surfaceof each of the first chips and an end of each of the conductive vias,wherein the end of each of the conductive vias protrudes from the topsurface of the corresponding first chip to form a through silicon via.Thereafter, second chips are respectively bonding onto theircorresponding first chips. A bottom surface of each of the second chipsfaces the corresponding first chip, each of the second chips has aplurality of pillar bumps on its bottom surface, and the pillar bumpselectrically connect their corresponding second chip with the throughsilicon vias.

In an embodiment, a first underfill encapsulating the first bumps isformed between the first chips and the circuit substrate after bondingthe first chips onto the top surface of the circuit substrate.

In an embodiment, the package process further comprises forming a secondmolding compound on the first molding compound after bonding the secondchips onto their corresponding first chips. The second molding compoundcovers the second chips.

In an embodiment, the package process further comprises forming a secondunderfill between each of the second chips and the corresponding firstchip after bonding the second chips onto their corresponding firstchips. The second underfill encapsulates the pillar bumps and the end ofeach of the through silicon vias.

Another semiconductor package including a circuit substrate, a packageunit and a first underfill is provided. The circuit substrate comprisesa top surface and a bottom surface opposite to the top surface. Thepackage unit is disposed on the top surface of the circuit substrate.The package unit comprises a first chip, a first molding compound, aplurality of first bumps, a second chip and a plurality of pillar bumps.The first chip has a top surface and a bottom surface opposite to eachother, and the bottom surface of the first chip faces the circuitsubstrate. The first chip has a plurality of through silicon vias,wherein an end of each of the through silicon vias protrudes from thetop surface of the first chip. The first molding compound covers thefirst chip, wherein a bottom surface of the first molding compound iscoplanar with the bottom surface of the first chip, and the firstmolding compound has an opening exposing the top surface of the firstchip and the end of each of the through silicon vias. The first bumpsare disposed between the first chip and the circuit substrate andelectrically connecting the through silicon vias with the circuitsubstrate. The second chip is disposed above the first chip, and thesecond chip has a bottom surface facing the first chip. The pillar bumpsare disposed on the bottom surface of the second chip and electricallyconnecting the second chip with the corresponding through silicon vias.

In an embodiment, the package structure further comprises a firstunderfill disposed between the package unit and the circuit substrate toencapsulate the first bumps.

In an embodiment, the package structure further comprises a secondmolding compound disposed on the first molding compound and covering thesecond chip.

In an embodiment, the package structure further comprises a secondunderfill disposed between the second chip and the first chip toencapsulate the pillar bumps and the end of each of the through siliconvias.

In an embodiment, a top surface of the first molding compound is higherthan the top surface of the first chip.

In an embodiment, a top surface of the first molding compound is higherthan the end of each of the through silicon vias.

In an embodiment, a top surface of the first molding compound has aheight difference H1 relative to the end of each of the through siliconvias, and a height H2 of the pillar bumps is greater than the heightdifference H1.

A package process is also provided herein. First, a carrier with anadhesive layer coated thereon is provided. Next, a plurality of firstchips is disposed on the adhesive layer, wherein a bottom surface ofeach of the first chips faces the carrier. Each of the first chips has aplurality of first bumps on the bottom surface of the first chip and aplurality of conductive vias. The first bumps are embedded into theadhesive layer. Then, a first molding compound is formed on the adhesivelayer to cover the adhesive layer and the first chips. Then, the firstmolding compound above each of the first chips is removed and thethickness of each of the first chips is reduced to expose a top surfaceof each of the first chips and an end of each of the conductive vias,wherein the end of each of the conductive vias protrudes from the topsurface of the corresponding first chip to form a through silicon via.Thereafter, second chips are respectively bonding onto theircorresponding first chips. A bottom surface of each of the second chipsfaces the corresponding first chip, and each of the second chips has aplurality of pillar bumps. The pillar bumps are disposed on the bottomsurface of the second chip and electrically connecting the correspondingsecond chip with the through silicon vias. Then, the carrier and theadhesive layer are removed to form a package unit array and the packageunit array are cut to obtain a plurality of package units. After that,one of the package units is bonded onto a top surface of a circuitsubstrate. The package unit is electrically connected to the circuitsubstrate through the corresponding first bumps. Then, the circuitsubstrate is cut.

In an embodiment, the package process further comprises forming a firstunderfill between the chip unit and the circuit substrate after bondingone of the package units onto the top surface of the circuit substrate.The first underfill encapsulates the first bumps.

In an embodiment, the package process further comprises forming a secondmolding compound on the first molding compound after bonding the secondchips onto their corresponding first chips, wherein the second moldingcompound covers the first molding compound.

In an embodiment, the package process further comprises forming a secondunderfill between each of the second chips and the corresponding firstchip after bonding the second chips onto their corresponding firstchips. The second underfill encapsulates the pillar bumps and the end ofeach of the through silicon vias.

As to the above, pillar bumps are adopted in the present invention toconnect an upper second chip and through silicon vias of a lower firstchip so as to control a gap between the first chip and the second chipby adjusting a height of the pillar bumps. In other words, the pillarbumps of the present invention compensate the height difference betweenthe first chip and a first molding compound surrounding the first chipso as to ensure the bondibility between the pillar bumps and thecorresponding through silicon vias and thereby improve the processyield. Furthermore, the pillar bumps maintain the gap between the secondchip and the first molding compound for allowing an underfill beingproperly filled into the space between the first chip and the secondchip.

In order to make the aforementioned and other features and advantages ofthe invention more comprehensible, embodiments accompanying figures aredescribed in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 illustrates a package structure according to an embodiment of thepresent invention.

FIGS. 2A through 2K illustrate a method for fabricating the packagestructure of FIG. 1.

FIGS. 3A and 3B illustrate a part of packaging process of the packagestructure of FIG. 1 according to another embodiment of the presentinvention.

FIGS. 4A and 4B illustrate a part of packaging process of the packagestructure of FIG. 1 according to further another embodiment of thepresent invention.

FIG. 5 illustrates a package structure according to another embodimentof the present invention.

FIGS. 6A through 6J illustrate a method for fabricating the packagestructure of FIG. 5.

FIGS. 7A and 7B illustrate a part of packaging process of the packagestructure of FIG. 5 according to another embodiment of the presentinvention.

FIGS. 8A and 8B illustrate a part of packaging process of the packagestructure of FIG. 5 according to further another embodiment of thepresent invention.

DESCRIPTION OF EMBODIMENTS

The present invention uses pillar bumps to connect an upper second chipand a lower first chip so as to control a gap between the first chip andthe second chip and overcome a height difference between the first chipand a molding compound surrounding the first chip caused by formingthrough silicon vias. The aforementioned concept can be applied tovarious stacked semiconductor device packages, and some packagestructures and package processes of stacked semiconductor device packageare illustrated in the following embodiments.

FIG. 1 illustrates a package structure according to an embodiment of thepresent invention. As shown in FIG. 1, the package structure 100 of thepresent embodiment comprises a circuit substrate 110, a first chip 120,a plurality of first bumps 130, a first underfill 140, a first moldingcompound 150, a second chip 160, a plurality of pillar bumps 170 and asecond underfill 180. The circuit substrate 110 has a top surface 110 aand a bottom surface 110 b opposite to the top surface 110 a. The firstchip 120 is disposed on the top surface 110 a of the circuit substrate110. In addition, a bottom surface 120 b of the first chip 120 faces thecircuit substrate 110, and the first chip 120 has a plurality of throughsilicon vias 122. An end 122 a of each of the through silicon vias 122protrudes from a top surface 120 a of the first chip 120.

Referring to FIG. 1, the first bumps 130 are disposed between the firstchip 120 and the circuit substrate 110 to electrically connecting thethrough silicon vias 122 with the circuit substrate 110. The underfill140 is disposed between the first chip 120 and the circuit substrate 110for encapsulating the first bumps 130. Moreover, the first moldingcompound 150 covers the entire top surface 110 a of the circuitsubstrate 110 and has an opening 152 exposing the top surface 120 a ofthe first chip 120 and the end 122 a of each of the through silicon vias122. Herein, the through silicon vias 122 are fabricated by grinding thefirst chip 120 and the first molding compound 150 above the first chip120 until a top surface of each of the through silicon vias 122 isexposed. Next, a selective etching process is performed to the firstchip 120 to protruding the end 122 a of each of the through silicon vias122 from the first chip 120. Herein, a top surface 150 a of the firstmolding compound 150 may be higher than the top surface 120 a of thefirst chip 120. Furthermore, the top surface 150 a of the first moldingcompound 150 may also be higher than the end 122 a of each of thethrough silicon vias 122.

The second chip 160 is disposed above the first chip 120, and a bottomsurface 160 b of the second chip 160 faces the first chip 120. Thepillar bumps 170 are disposed on the bottom surface 160 b of the secondchip 160 and electrically connecting the second chip 160 with thecorresponding through silicon vias 122. The pillar bumps 170 may bebonded with the corresponding through silicon vias 122 by for example asolder material 128. The second underfill 180 is disposed between thesecond chip 160 and the first chip 120 to encapsulate the pillar bumps170 and the end 122 a of each of the through silicon vias 122.Furthermore, the package structure 100 may comprise a second moldingcompound 190 disposed on the first molding compound 150 and covering thesecond chip 160 and the second underfill 180. The circuit substrate 110may be provided with a plurality of solder balls 192 on its bottomsurface 110 b.

In the package structure 100 of the present embodiment, the top surface150 a of the first molding compound 150 may have a height difference H1relative to the end 122 a of each of the through silicon vias 122, whilethe height H2 of the pillar bumps 170 is greater than the heightdifference H1 to overcome the height difference H1 and thereby ensure aneffective bonding between the pillar bumps 170 and their correspondingthrough silicon vias 122. A material of the pillar bumps 170 may becopper, gold, aluminum or other appropriate conductive materials.

In addition, a size of the second chip 160 is greater than that of thefirst chip 120. Since the height H2 of the pillar bumps 170 is greaterthan the height difference H1 between the top surface 150 a of the firstmolding compound 150 and the end 122 a of each of the through siliconvias 122, the second chip 160 can be kept away from the top surface 150a of the first molding compound 150 such that the second underfill 180can be properly filled into the space between the first chip 120 and thesecond chip 160 and the space between the second chip 160 and the firstmolding compound 150. Certainly, in other embodiments of the presentinvention, the size of the second chip 160 may also be smaller than thatof the first chip 120. The sizes of the first chip 120 and the secondchip 160 are not limited in the present invention.

FIGS. 2A through 2K illustrate a method for fabricating the packagestructure 100 of FIG. 1. For a clear description, FIGS. 2A through 2Kshow only the package process of a unit in a partial region.Practically, the package process of the present embodiment may be awafer level package process, wherein the package process is performed toa plurality of units arranged in an array on a carrier to form aplurality of package structures 100 as show in FIG. 1.

Firstly, referring to FIG. 2A, the circuit substrate 110 is disposed ona carrier 102, wherein the bottom surface 110 b of the circuit substrate110 is bonded with the carrier 102 via an adhesive layer 104. Thecarrier 102 may be a wafer or other applicable substrates. Next,referring to FIG. 2B, a first underfill 140 is coated on the top surface110 a of the substrate 110. The first underfill 140 may be athermal-cured material. And, referring to FIG. 2C, a thermal pressinghead 702 obtains the first chip 120 and bonds the first chip 120 to thecircuit substrate 110 by flip-chip technique. The bottom surface 120 bof the first chip 120 faces the circuit substrate 110. Each of the firstchips 120 has a plurality of first bumps 130 on the bottom surface 120 band a plurality of conductive vias 122′.

Afterwards, referring to FIG. 2D, each of the first bumps 130 iselectrically connected to the corresponding conductive vias 122′ and thecircuit substrate 110. The first underfill 140 encapsulates the firstbumps 130. And, the first molding compound 150 is formed to cover thetop surface 110 a of the circuit substrate 110, the first chip 120 andthe first underfill 140. Then, referring to FIG. 2E, the first moldingcompound 150 above the first chip 120 is removed and the thickness ofthe first chip 120 is reduced to expose the top surface 120 a of thefirst chip 120 and the end 122 a of each of the conductive vias 122′ bygrinding, selective etching or other applicable processes, wherein theend 122 a of each of the conductive vias 122′ protrudes from the topsurface 120 a of the corresponding first chip 120 to form the throughsilicon via 122.

Next, referring to FIG. 2F, a surface treatment is performed to the end122 a of each of the through silicon vias 122 and a solder material 128(or a nickel/gold stacked layer) can be formed on the end 122 a, so asto improve the bondibility between the pillar bumps 170 (as shown inFIG. 2H) and the through silicon vias 122 in the sequent bondingprocess. Then, referring to FIG. 2G, the second underfill 180 is formedon the top surface 120 a of the first chip 120. The second underfill 180may be a thermal-cured material.

Then, referring to FIG. 2H, a thermal pressing head 704 obtains thesecond chip 160 and bonds the second chip 160 to the first chip 120 byflip-chip technique. The bottom surface 160 b of the second chip 160faces the first chip 120. In addition, the second chip 160 is providedwith the pillar bumps 170 on its bottom surface 160 b. Afterwards,referring to FIG. 2I, the pillar bumps 170 are bonded to thecorresponding through silicon vias 122 through the solder material 128,so as to electrically connect the second chip 160 with the first chip120. The second underfill 180 encapsulates the pillar bumps 170 and theend 122 a of each of the through silicon vias 122. Furthermore, thepresent embodiment may form the second molding compound 190 on the firstmolding compound 150 as shown in FIG. 2I after accomplishing the step ofFIG. 2H. The second molding compound 190 covers the second chip 160 andthe second underfill 180.

However, in another embodiment, the second underfill 190 need not beformed.

After the above steps, the circuit substrate 110 and the carrier 102 canbe separated from each other as shown in FIG. 2J. And, referring to FIG.2K, a plurality of solder balls 192 may be formed on the bottom surface110 b of the circuit substrate 110, and then the package structure inarray profile can be singulated to obtain a plurality of packagestructures 100 as show in FIG. 1. As to the above, lateral surfaces ofthe substrate 110, the first molding compound 150 and the second moldingcompound 190 are coplanar with one another.

FIGS. 2A to 2K illustrate the package process forming the firstunderfill 140 before bonding the first chip 120 with the circuitsubstrate 110 by flip-chip technique. In addition, the second underfill180 is formed before bonding the second chip 160 with the first chip120.

Nevertheless, the present invention should not be construed as limitedto the aforementioned embodiments.

FIGS. 3A and 3B illustrate a part of packaging process of the packagestructure of FIG. 1 according to another embodiment of the presentinvention. Following the step illustrated in FIG. 2A, the process ofFIG. 3A is proposed by bonding the first chip 120 to the circuitsubstrate 110 by flip-chip technique first. Then, as shown in FIG. 3B,the first underfill 140 is filled between the first chip 120 and thecircuit substrate 110 to encapsulate the first bumps 130. After the stepof FIG. 3B, the step of FIG. 2D as illustrated above can be performed.

FIGS. 4A and 4B illustrate a part of packaging process of the packagestructure of FIG. 1 according to further another embodiment of thepresent invention. Following the step illustrated in FIG. 2F, theprocess of FIG. 4A is proposed by bonding the second chip 160 with thefirst chip 160 by flip-chip technique first. Then, as shown in FIG. 4B,the second underfill 180 is filled between the second chip 160 and thefirst chip 120 to encapsulate the pillar bumps 170 and the end 122 a ofeach of the through silicon vias 122. After the step of FIG. 4B, thestep of FIG. 2I as illustrated above can be performed.

FIG. 5 illustrates a package structure according to another embodimentof the present invention. As shown in FIG. 5, a semiconductor package500 comprises a circuit substrate 510, a package unit 512 and a firstunderfill 540 is provided. The circuit substrate 510 has a top surface510 a and a bottom surface 510 b opposite to the top surface 510 a. Thepackage unit 512 is disposed on the top surface 510 a of the circuitsubstrate 510. The package unit 512 comprises a first chip 520, a firstmolding compound 550, a plurality of first bumps 530, a second chip 560,a plurality of pillar bumps 570 and a second underfill 580. The firstchip 520 has a top surface 520 a and a bottom surface 520 b opposite toeach other, and the bottom surface 520 b of the first chip 520 faces thecircuit substrate 510.

The first chip 520 has a plurality of through silicon vias 522. An end522 a of each of the through silicon vias 522 protrudes from the topsurface 520 a of the first chip 520. The first molding compound 550encapsulates the first chip 520. A bottom surface 550 b of the firstmolding compound 550 is coplanar with the bottom surface 520 b of thefirst chip 520, and the first molding compound 550 has an opening 552exposing the top surface 520 a of the first chip 520 and the end 522 aof each of the through silicon vias 522. The first bumps 530 aredisposed between the first chip 520 and the circuit substrate 510 andelectrically connecting the through silicon vias 522 with the circuitsubstrate 510.

Herein, the through silicon vias 522 are fabricated by grinding thefirst chip 520 and the first molding compound 550 above the first chip120 until a top surface of each of the through silicon vias 522 isexposed. Then, a selective etching process is performed to the firstchip 520 to protruding the end 522 a of each of the through silicon vias522 from the first chip 520. Thus, the top surface 550 a of the firstmolding compound 550 may be higher than the top surface 520 a of thefirst chip 520. Furthermore, the top surface 550 a of the first moldingcompound 550 may also be higher than the end 522 a of each of thethrough silicon vias 522.

The second chip 560 is disposed above the first chip 520. The bottomsurface 560 b of the second chip 560 faces the first chip 520. Thepillar bumps 570 are disposed on the bottom surface 560 b of the secondchip 560 and electrically connecting the second chip 560 with thecorresponding through silicon vias 522. The pillar bumps 570 may bebonded with the corresponding through silicon vias 522 by for example asolder material 528. The second underfill 580 is disposed between thesecond chip 560 and the first chip 520 to encapsulate the pillar bumps570 and the end 522 a of each of the through silicon vias 522. Theunderfill 540 is disposed between the package unit 512 and the circuitsubstrate 510 to encapsulate the first bumps 530. Furthermore, thepackage structure 500 may comprise a second molding compound 590disposed on the first molding compound 550 and covering the second chip560 and the second underfill 580. The circuit substrate 510 may beprovided with a plurality of solder balls 592 on its bottom surface 510b.

In the package structure 500 of the present embodiment, the top surface550 a of the first molding compound 550 may have a height difference H3relative to the end 522 a of each of the through silicon vias 522, whilethe height H4 of the pillar bumps 570 is greater than the heightdifference H3 to overcome the height difference H3 and thereby ensure aneffective bonding between the pillar bumps 570 and their correspondingthrough silicon vias 522.

In addition, a size of the second chip 560 is greater than that of thefirst chip 520. Since the height H4 of the pillar bumps 570 is greaterthan the height difference H3 between the top surface 550 a of the firstmolding compound 550 and the end 522 a of each of the through siliconvias 522, the second chip 560 can be kept away from the top surface 550a of the first molding compound 550 such that the second underfill 580can be properly filled into the space between the first chip 520 and thesecond chip 560 and the space between the second chip 560 and the firstmolding compound 550. Certainly, in other embodiments of the presentinvention, the size of the second chip 560 may also be smaller than thatof the first chip 520. The sizes of the first chip 520 and the secondchip 560 are not limited in the present invention.

FIGS. 6A through 6J illustrate a method for fabricating the packagestructure 500 of FIG. 5. For a clear description, FIGS. 6A through 6Jshow only the package process of a unit in a partial region.Practically, the package process of the present embodiment may be awafer level package process, wherein the package process is performed toa plurality of units arranged in an array on a carrier to form aplurality of package structures 500 as show in FIG. 5.

First, referring to FIG. 6A, a carrier 502 with an adhesive layer 504coated thereon is provided. Next, the first chip 520 is disposed on theadhesive layer 504. The bottom surface 520 b of the first chip 520 facesthe carrier 502. The first chip 520 has a plurality of first bumps 530on the bottom surface 520 b and a plurality of conductive vias 522′,wherein the first bumps 530 are embedded into the adhesive layer 504.

Then, referring to FIG. 6B, a first molding compound 550 is formed onthe adhesive layer 504 to cover the adhesive layer 504 and the firstchip 520. Next, referring to FIG. 6C, the first molding compound 550above the first chip 520 is removed and the thickness of the first chip520 is reduced to expose the top surface 520 a of the first chip 520 andthe end 522 a of each of the conductive vias 522′, wherein the end 522 aof each of the conductive vias 522′ protrudes from the top surface 520 aof the corresponding first chip 520 to form the through silicon via 522.

Then, referring to FIG. 6D, a surface treatment is performed to the end522 a of each of the through silicon vias 522 and a solder material 528(or a nickel/gold stacked layer) can be formed on the end 522 a, so asto improve the bondibility between the pillar bumps 570 (as shown inFIG. 6F) and the through silicon vias 522 in the sequent bondingprocess. Afterwards, referring to FIG. 6E, the second underfill 580 isformed on the top surface 520 a of the first chip 520. The secondunderfill 580 may be a thermal-cured material.

Then, referring to FIG. 6F, a thermal pressing head 802 obtains thesecond chip 560 and bonds the second chip 560 to the first chip 520 byflip-chip technique. The bottom surface 560 b of the second chip 560faces the first chip 520. In addition, the second chip 560 is providedwith the pillar bumps 570 on its bottom surface 560 b. Next, referringto FIG. 6G, the pillar bumps 570 are bonded to the corresponding throughsilicon vias 522 through the solder material 528, so as to electricallyconnect the second chip 560 with the first chip 520. The secondunderfill 580 encapsulates the pillar bumps 570 and the end 522 a ofeach of the through silicon vias 522. Furthermore, the presentembodiment may form the second molding compound 590 on the first moldingcompound 550 as shown in FIG. 6G after accomplishing the step of FIG.6F. The second molding compound 590 covers the second chip 560 and thesecond underfill 580.

However, in another embodiment, the second underfill 590 need not beformed.

After the above steps, the carrier 502 and the adhesive layer 504 canfurther be removed to form a package unit array 511. And, the firstbumps 530 previously embedded into the adhesive layer 504 are nowexposed. Then, the package unit array 511 is cut to obtain a pluralityof package unit 512 as shown in FIG. 6J.

Next, referring to both FIGS. 6I and 6J, a first underfill 540 is coatedon the top surface 510 a of the substrate 510. The first underfill 540may be a thermal-cured material. And, a thermal pressing head 804obtains the package unit 512 and bonds the package unit 512 to thecircuit substrate 510 by flip-chip technique.

The bottom surface 520 b of the first chip 520 faces the circuitsubstrate 510. The package unit 512 is electrically connected to circuitsubstrate 510 through the first bumps 530 on the bottom surface 520 b ofthe first chip 520, and the first underfill 540 encapsulates the firstbumps 530. A plurality of solder balls 592 may be formed on the bottomsurface 510 b of the circuit substrate 510, and then the packagestructure in array profile can be singulated to obtain a plurality ofpackage structures 500 as shown in FIG. 5.

FIGS. 6A to 6J illustrate the package process filling the secondunderfill 580 between the first chip 520 and the second chip 560 beforebonding the second chip 560 with the first chip 520 by flip-chiptechnique. In addition, the first underfill 540 is filled between thepackage unit 512 and the circuit substrate 510 before bonding thepackage unit 512 with the circuit substrate 510 by flip-chip technique.

Nevertheless, the present invention should not be construed as limitedto the aforementioned embodiments.

FIGS. 7A and 7B illustrate a part of packaging process of the packagestructure of FIG. 5 according to another embodiment of the presentinvention. Following the step illustrated in FIG. 6D, the process ofFIG. 7A is proposed by bonding the second chip 560 with the first chip520 by flip-chip technique first. Then, as shown in FIG. 7B, the secondunderfill 580 is filled between the second chip 560 and the first chip520 to encapsulate the pillar bumps 570 and the end 522 a of each of thethrough silicon vias 522. After the step of FIG. 7B, the step of FIG. 6Gas illustrated above can be performed.

FIGS. 8A and 8B illustrate a part of packaging process of the packagestructure of FIG. 5 according to further another embodiment of thepresent invention. Following the step illustrated in FIG. 6H, theprocess of FIG. 8A is proposed by bonding the package unit 512 to thecircuit substrate 510 by flip-chip technique first. Then, as shown inFIG. 8B, the first underfill 540 is filled between the package unit 512and the circuit substrate 510 to encapsulate the first bumps 530. Inaddition, a plurality of solder balls 592 may be formed on the bottomsurface 510 b of the circuit substrate 510, and then the packagestructure in array profile can be singulated to obtain a plurality ofpackage structures 500 as show in FIG. 5.

Therefore, the present invention provides no limitation in whetherforming the underfill or performing the flip-chip bonding first, and thesizes of the upper second chip and the lower first chip are notrestricted. The pillar bumps are adopted to connect the upper secondchip and the through silicon vias of the lower first chip so as tocontrol a gap between the first chip and the second chip by adjustingthe height of the pillar bumps and thereby overcome the heightdifference between the first chip and the first molding compoundsurrounding the first chip. The second chip can be reliably andeffectively bonded with the through silicon vias of the first chip inthe stacked semiconductor device package, and the process yield isimproved. Furthermore, the pillar bumps maintain the gap between theupper second chip and the first molding compound for allowing anunderfill being properly filled into the space between the first chipand the second chip.

Although the invention has been described with reference to the aboveembodiments, it will be apparent to one of the ordinary skill in the artthat modifications to the described embodiment may be made withoutdeparting from the spirit of the invention. Accordingly, the scope ofthe invention will be defined by the attached claims not by the abovedetailed descriptions.

1. A package structure, comprising: a circuit substrate, comprising atop surface and a bottom surface opposite to the top surface; a firstchip, disposed on the top surface of the circuit substrate, wherein thefirst chip has a top surface and a bottom surface opposite to eachother, the bottom surface of the first chip faces the circuit substrate,the first chip has a plurality of through silicon vias, and an end ofeach of the through silicon vias protrudes from the top surface of thefirst chip; a plurality of first bumps, disposed between the first chipand the circuit substrate and electrically connecting the throughsilicon vias with the circuit substrate; a first molding compound,covering the top surface of the circuit substrate and having an openingexposing the top surface of the first chip and the end of each of thethrough silicon vias; a second chip, disposed above the first chip, thesecond chip having a bottom surface facing the first chip, wherein asize of the second chip is greater than that of the first chip; and aplurality of pillar bumps, disposed on the bottom surface of the secondchip and electrically connecting the second chip with the correspondingthrough silicon vias wherein a top surface of the first molding compoundhas a height difference H1 relative to the end of each of the throughsilicon vias, and a height H2 of the pillar bumps is greater than theheight difference H1.
 2. The package structure according to claim 1,further comprising a first underfill disposed between the first chip andthe circuit substrate to encapsulate the first bumps.
 3. The packagestructure according to claim 2, wherein the first underfill comprises athermal-cured material.
 4. The chip package as claimed in claim 1,further comprising a second molding compound disposed on the firstmolding compound and covering the second chip.
 5. The package structureaccording to claim 4, further comprising a first underfill disposedbetween the first chip and the circuit substrate to encapsulate thefirst bumps.
 6. The package structure according to claim 5, furthercomprising a second underfill disposed between the second chip and thefirst chip to encapsulate the pillar bumps and the end of each of thethrough silicon vias.
 7. The package structure according to claim 1,further comprising a second underfill disposed between the second chipand the first chip to encapsulate the pillar bumps and the end of eachof the through silicon vias.
 8. The package structure according to claim7, wherein the first underfill comprises a thermal-cured material. 9.The package structure according to claim 1, wherein a lateral surface ofthe circuit substrate and a lateral surface of the first moldingcompound are coplanar with each other.
 10. The package structureaccording to claim 4, wherein a lateral surface of the circuitsubstrate, a lateral surface of the first molding compound, and alateral surface of the second molding compound are coplanar with oneanother.
 11. The package structure according to claim 1, furthercomprises a plurality of solder balls disposed at a bottom of thecircuit substrate.
 12. The package structure according to claim 1,wherein a periphery of the second chip is located above the top surfaceof the first molding compound.
 13. A package structure, comprising: acircuit substrate, comprising a top surface and a bottom surfaceopposite to the top surface; a package unit, disposed on the top surfaceof the circuit substrate, the package unit comprising: a first chip,having a top surface and a bottom surface opposite to each other, thebottom surface of the first chip faces the circuit substrate, the firstchip has a plurality of through silicon vias, and an end of each of thethrough silicon vias protrudes from the top surface of the first chip; afirst molding compound, covering the first chip, wherein a bottomsurface of the first molding compound is coplanar with the bottomsurface of the first chip, and the first molding compound has an openingexposing the top surface of the first chip and the end of each of thethrough silicon vias; a plurality of first bumps, disposed between thefirst chip and the circuit substrate and electrically connecting thethrough silicon vias with the circuit substrate; a second chip, disposedabove the first chip, the second chip having a bottom surface facing thefirst chip, wherein a size of the second chip is greater than that ofthe first chip; and a plurality of pillar bumps, disposed on the bottomsurface of the second chip and electrically connecting the second chipwith the corresponding through silicon vias, wherein a distance betweenthe bottom surface of the second chip and the top surface of the firstchip is greater than that between a top surface of the first moldingcompound and the top surface of the first chip.
 14. The packagestructure as claimed in claim 13, wherein a size of the circuitsubstrate is greater than that of the package unit.
 15. The packagestructure according to claim 13, further comprising a first underfilldisposed between the package unit and the circuit substrate toencapsulate the first bumps.
 16. The package structure as claimed inclaim 13, further comprising a second molding compound disposed on thefirst molding compound and covering the second chip.
 17. The packagestructure according to claim 16, further comprising a first underfilldisposed between the package unit and the circuit substrate toencapsulate the first bumps.
 18. The package structure according toclaim 17, further comprising a second underfill disposed between thesecond chip and the first chip to encapsulate the pillar bumps and theend of each of the through silicon vias.
 19. The package structureaccording to claim 16, wherein a lateral surface of the first moldingcompound and a lateral surface of the second molding compound arecoplanar with each other.
 20. The package structure according to claim13, further comprising a second underfill disposed between the secondchip and the first chip to encapsulate the pillar bumps and the end ofeach of the through silicon vias.